IC Layout Engineer - San Jose, CA

Description
You will be doing substrate design in FBAR filters and mmW active circuits 2/3 or your time. In this capacity you will be working as part of a product design team integrating IC die into final products by designing the substrate for the product on which the IC die resides. The other 1/3 of your time you will be doing IC tape-out by working closely with IC design teams to assist with DRC & LVS, perform layout cleanup, gather layout cells and compose reticle arrays, organize mask review meetings, create final GDS data, generate mask submission documentation, then interface with internal Reticle Service Team to submit mask job.

Qualifications
• B.A. or B.S in Electrical Engineering, Computer Science or Mathematics
• 10+ years of IC layout & tape-out experience in an RF/Microwave/mmWave R&D environment.
• Strong Cadence Virtuoso Layout and Assura or DIVA DRC/LVS skills.
• Strong LINUX and Windows user-level skills.
• Excellent written and verbal communication skills.
• Positive attitude, with a desire to learn and contribute in a fast paced global team.